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销售安立 MP1764C 误码仪

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产品参数

选件 是否计量 发货周期 保修时间 成色
5天 90天 8成新
所在地 机身号 状态 资料下载
深圳市 完好
更新日期:2026-01-07
联系电话:0755-86016691

* 产品描述

产品描述
安立 MP1764C 是一款归属于 MP1760X 系列的 12.5G 误码检测器,常与 MP1763C 脉冲码型发生器搭配组成误码率测试系统(BERT),主要用于高速传输设备和器件的性能评估,该设备的工作频率范围覆盖 50MHz - 12.5GHz,能适配多种高速传输标准下的测试需求,涵盖 STM - 64/OC - 192、10G 以太网、OTU - 2 以及 4.25G 光纤通道等主流高速传输场景。它支持 0.25 - 2Vpp 的时钟与数据信号幅度调节,且偏移量可在 2V 范围内调整,同时时钟输入延迟可调范围为 - 500ps 至 + 500ps,便于开展幅度、偏移容限及时间相关特性测试。
产品特点
测试便捷高效:具备一键自动搜索功能,可快速设定输入阈值和相位的最优值,省去复杂的手动调试步骤,大幅简化操作流程。在帧模式下,能在短时间内完成 8Mbit 码型的同步,且误码检测间隔最短可达 0.1 秒,测试效率大幅提升。
适配特殊场景需求:作为 12.5G 误码率测试系统,它拥有特殊的差分输入和 1/4 差分输出设计,这一特性恰好契合存储区域网络(SAN)市场设备的应用需求。同时还支持 4.25G 时钟数据恢复功能,可完美适配光纤通道相关应用的测试。

详细信息

Product Description
The Anritsu MP1764C is a 12.5G bit error detector belonging to the MP1760X series. It is often used in combination with the MP1763C pulse waveform generator to form a bit error rate testing system (BERT), mainly for the performance evaluation of high-speed transmission equipment and components. The operating frequency range of this device covers 50MHz - 12.5GHz, and it can meet the testing requirements of various high-speed transmission standards, including STM - 64/OC - 192, 10G Ethernet, OTU - 2, and 4.25G optical channels, covering mainstream high-speed transmission scenarios. It supports 0.25 - 2Vpp amplitude adjustment for both clock and data signals, and the offset can be adjusted within the 2V range. The delay of the clock input can be adjusted within the range of - 500ps to + 500ps, facilitating the testing of amplitude, offset tolerance, and time-related characteristics.
Product features
Test is convenient and efficient: It has a one-click automatic search function, which enables quick setting of the optimal input threshold and phase values, eliminating the need for complex manual debugging steps and significantly simplifying the operation process. In frame mode, it can complete the synchronization of 8Mbit code types within a short period of time, and the error detection interval can be as short as 0.1 seconds, greatly improving the test efficiency.
Adapted to special scenario requirements: As a 12.5G bit error rate testing system, it has a special differential input and 1/4 differential output design. This feature precisely meets the application requirements of equipment in the storage area network (SAN) market. It also supports 4.25G clock data recovery function, which can perfectly adapt to the testing of fiber channel-related applications.

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