Product Description:
The J-BERT N4903B high-performance serial BERT provides the most complete jitter tolerance test for embedded and forward clocked devices.
It is the ideal choice for R&D and validation teams characterizing and stressing chips and transceiver modules that have serial I/O ports up to 7 Gb/s, 12.5Gb/s or 14.2 Gb/s. It can characterize a receiver’s jitter tolerance and is designed to prove compliance to today’s most popular serial bus standards, such as:
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PCI Express® See Measurement Solution Example: PCIe 3.0 Receiver Test
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SATA/SAS
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DisplayPort
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USB SuperSpeed
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Fibre Channel
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QPI
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Memory buses, such as fully buffered DIMM2
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Backplanes, such as CEI
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10 GbE/ XAUI
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XFP/XFI, SFP+
Features：
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Data rates 150 Mb/s to 7 Gb/s or to 12.5 Gb/s pattern generator and error detector. Option to extended data rate to 14.2 Gb/s for pattern generator.
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>0.5 UI calibrated, compliant and integrated jitter injection: RJ, RJ-LF, RJ-HF, PJ1, PJ2, SJ, BUJ, ISI, sinusoidal interference, triangular and arbitrary SSC and residual SSC
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Excellent signal performance and sensitivity
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Built-in clock data recovery with tunable and compliant loop bandwidth
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Half-rate clocking with variable duty cycle for forwarded clocked devices
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Measures BER, BERT Scan, TJ with RJ/DJ separation, eye diagram, eye mask, BER contour, automated jitter tolerance, pattern capture, frame error rate (FER), or symbol error rate (SER) coded and retimed data streams
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Two adjustable data outputs with independent PRBS and pattern with 120 block pattern sequencer
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All options are retrofittable and upgrade from N4903A possible
服务热线：0755－86016691 电话：13715327187 传真：0755-86641139-816
