描述
去加重技术适合在以千兆位数据速率传输数字电信号的过程中使用。去加重是一个信号预失真，旨在补偿在 PC 电路板轨迹、背板或长电缆上以千兆位速率传输电信号时引起的信号质量下降。鉴于下一代串行总线标准的速度将超过 5 Gb/s，工程师将需要进行复杂的去加重和多分接有限脉冲响应（FIR）过滤。
全新 N4916B 去加重信号转换器使研发和测试工程师能够精确地仿真发射机去加重。
N4916B 可使用 1 个前光标（pre-cursor）和 2 个后光标（post-cursor）仿真发射机去加重，并独立调节高达 12.0 dB 的去加重电平。通过直流耦合，它能够容忍训练序列中常出现的非平衡码型流。当使用数据和时钟信号上的抖动进行激励时，N4916B 不会对抖动造成影响，能够仿真期望接收机会容忍的真实去加重和抖动条件。去加重还可补偿由电缆、夹具或测试仪中的测试电路板引起的失真，从而获得更精确的器件表征结果。
N4916B 的时钟倍频选件提供什么功能？
它与 N4916A 的主要差别是什么？
Overview and Features
The Keysight N4916B de-emphasis signal converter enables R&D and test engineers to accurately emulate transmitter de-emphasis.
The N4916B can emulate transmitter de-emphasis with one pre- and two post-cursors and individually adjustable de-emphasis levels of up to 12.0 dB. With its DC coupling, it tolerates unbalanced pattern streams that often occur in training sequences. The N4916B is transparent to jitter when stimulated with jitter on data and clock signals, enabling emulation of real-world de-emphasis and jitter conditions that a receiver is expected to tolerate. De-emphasis can also compensate for distortions caused by cables, fixtures, or test boards in the test set for more precise device characterization results.
The de-emphasis signal converter can operate as a front end for J-BERT N4903B, ParBERT, or other gigabit pattern generators. Users can control it via a USB interface from the J-BERT N4903B user interface or a standalone user interface with programming examples.
The clock multiplier option enables error counting and error analysis of devices using half-rate clocking. The full-rate clock is needed to use the error, eye, or jitter analysis capabilities of J-BERT N4903B.
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